Simulation and Performance Estimation for the Rewrite Rule Machine
نویسندگان
چکیده
The Rewrite Rule Machine (RRM) is a massively parallel machine being developed at SRI International that combines the power of SIMD with the generality of MIMD. The RRM exploits both extremely ne-grain and coarse-grain parallelism, and is based on an abstract model of computation that eases creating and porting parallel programs. In particular, the RRM can be programmed very naturally with very high-level declarative languages featuring implicit parallelism. This paper gives an overview of the RRM's architecture and discusses performance estimates based on very detailed register-level simulations at the chip level together with more abstract simulations and modeling for higher levels.
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